An electronic circuit is chemically and physically integrated into a substrate such as a silicon wafer by patterning regions below the surface of the substrate, and by patterning layers of various materials over the surface of the substrate. These regions and layers can be conductive for conductor and resistor fabrication, or insulative for insulator and capacitor fabrication. They can also be of differing conductivity types, which is essential for transistor and diode fabrication. Degrees of resistance, capacitance, and conductivity are controllable, as are the physical dimensions and locations of the patterned regions and layers, making circuit integration possible. Fabrication can be quite complex and time consuming, and therefore expensive. It is thus a continuing effort of those in the semiconductor fabrication business to reduce fabrication times and costs of such devices in order to increase profits. Any simplified processing step or combination of processes at a single step becomes a competitive advantage.
A situation where a process simplification is desirable is in the anisotropic etch of a layer of oxide on a layer of silicide on a layer of polycrystalline silicon (poly). In this disclosure, "oxide" denotes an oxide of silicon and "silicide" refers to tungsten silicide. 37 Polycide" denotes a silicide-over-poly combination. Oxide is an insulator with dielectric properties. Poly is resistive in nature, but is made less resistive when doped with an element having less or more than four valence electrons (depending on whether the poly defines a P-channel or N-channel device), or when layered with conductive silicide. "Anisotropic etch" refers to a directionally preferential etch in which the etch rate in one direction, usually vertically, greatly exceeds the etch rate in other directions. This is typically accomplished by plasma etching in which the plasma energy erodes substrate material in a direction established by the ion flow. Advantages of anisotropic etching include reduced sidewall erosion, reduced undercutting, and improved line width control. This contrasts with isotropic etching, wherein etching is achieved at a more uniform rate across all exposed surfaces.
An oxide/silicide/poly sandwich structure presents a difficult etching task, particularly with an additional mask layer of photoresist (resist), which must be the case if patterning is desired. The difficulty is partly due to the distinct differences in the way oxide and polycide are etched, particularly with resist still present on top of the structure.
Both oxide and polycide can be etched using a parallel plate plasma reactor. However, an oxide is typically etched in fluorine deficient fluorocarbon based plasmas, whereas silicide and poly can be etched in fluorine or chlorine based discharges. Reactor cathode materials may also differ: for oxide etch, an erodible cathode such as graphite or silicon is often used to provide a source of carbon or silicon for etch selectivity, whereas for polycide etch, an inert cathode is
preferred, especially when utilizing chlorine gas (Cl.sub.2) for selectivity. If a single-chamber process were attempted using conventional art to etch an oxide/silicide/poly sandwich structure, the erodible cathode required for oxide etch would be destroyed by the chlorine required for polycide etch. Using conventional methods, the two steps are incompatible.
Oxide etch in general is fairly well understood, given a universal need for a vertical profile. This vertical profile is realized primarily by ion induced reaction with the oxide, coupled with normal incidence of the ions onto the oxide surface. The amount and energy of these ions are primarily controlled by the reactor's RF power and gap. Generally, a fluorocarbon-based gas mixture is introduced at a low pressure into the etch chamber. The exact gas composition is chosen, and an erodible cathode is used to scavenge excessive fluorine radicals so that the fluorine-to-carbon ratio is near, but not beyond, the so-called polymerization point. Under these conditions, when a plasma is ignited, the fluorocarbons are dissociated and release fluorine radicals and CF.sub.x species. Although fluorine radicals etch oxide, they do so very slowly: the primary etchant for oxide is considered to be the CF.sub.x species. Some of these species diffuse to the oxide surface where, with the assistance of ion bombardment, they react with the oxide and release volatile byproducts SiF.sub.4, CO, and CO.sub.2. In addition, some of the CF.sub.x species react with each other to form fluorocarbon polymers. Polymer that forms on horizontal surfaces is removed by vertical ion bombardment. Polymer that forms on vertical sidewalls during this oxide etch is not significantly degraded by the bombardment, and actually serves a useful purpose by protecting the oxide sidewalls from attack by the etchant species. This sidewall protection enables the achievement of vertical profiles, adjustable by varying the fluorine-to-carbon ratio. As the cathode is eroded, the quantity of available fluorine radicals is reduced. Therefore, a polymer-producing gas such as CHF.sub.3 is balanced against a fluorine producing gas such as CF.sub.4 to provide proper selectivity, with assistance to sidewall protection.
Two methods are conventionally used to etch an oxide/ silicide/poly sandwich structure. Both methods use separate reactors: one for the oxide etch, and one for the polycide etch.
In the first method, the oxide etch reactor uses fluorocarbon-based chemistry, high RF power, and an erodible cathode. The sidewalls remain straight and the etch stops soon after entering the silicide. After oxide etch, the wafer is removed from the chamber and the resist is stripped (piranha etch). The silicide/poly sandwich is then etched in a poly etch reactor, using an inert cathode. Both etches are anisotropic.
The second method uses the same principles as the first, except that there are two reactors in one machine. The two reactors are configured as separate oxide and polycide reactors having a common vacuum transfer area, so that a wafer can be transferred in a vacuum from the oxide reactor to the polycide reactor, thus minimizing additional handling. The resist is generally not removed prior to polycide etch in this method. This is sometimes referred to as "in situ" since the wafers never leave the vacuum of one machine. However, they are not truly in situ in the sense that two etch chambers are used. A one chamber in situ etch process has recently been developed by Micron Technology, Inc. and is described in U.S. Pat. No. 5,094,712, which is incorporated herein by reference.
As the feature size of semiconductor devices such as dynamic random access memories (DRAMs) continues to decrease it becomes increasingly important to minimize irregularities during the formation of the device. For example, cell gate widths approaching 0.5 microns require that vertical sidewalls be strictly maintained to provide adequate area to store a charge. Advances in process technology which decrease surface irregularities are desirable.